Intel Core Duo and Core Solo processors

Along with the new 65-nm process technology used in the production of Core Duo (Yonah) chips, which allowed to reduce the dimensions of transistors and increase the density of positioning components on the chip, processors built on the Yonah core offer a number of the following characteristics:

• Parallel execution of task branches on two cores with the processor resources distributed
• Integrated L1 cache: 32 K for instructions and 32 K for data
• L2 cache - Intel Smart Cache, 2 MB in size, with support for the Advanced Transfer Cache architecture that provides for efficient usage of cache memory and the processor bus to boost performance of the 2-core system and reduce the power consumption
• Intel Digital Media Boost - a new item in the processor architecture to optimize processing of instructions of the Streaming SIMD Extensions 2 class (SSE2) and Streaming SIMD Extensions 3 (SSE3), which offers a much higher performance for resource-intensive tasks - processing audio/video, images, 3D graphics, or scientific computations
• The Advanced Branch Prediction architecture which combines three types of prediction–Global, Bi-Modal, and Loop Detector. The processors selects the most optimum algorithm automatically, which cuts down the number of mis-predicted branching
• System bus of 667 MHz speed, optimized for power consumption - uses the Source-Synchronous Transfer (SST) protocol for transferring addresses and data synchronously, which provides for increased bandwidth and data transmission at a speed as 4 times as much of the system bus speed. The Advanced Gunning Transceiver Logic (AGTL+), a version of the GTL+ technology, with additional power-saving
• The Intel Dynamic Power Coordination with the Dynamic Bus Parking feature - "on-demand" coordination of the cores performance. Advanced features for reducing the power consumption due to the Dynamic Bus Parking allow cutting down the chipset's power consumption while the processor is running at reduced clock speeds. The Intel Dynamic Power Coordination allows each core to switch to the Halt, Stop Clock, and Deep Sleep states dynamically, and in the 2-core mode – synchronously to the Deeper and Enhanced Deeper Sleep modes. The distributed logic of the chip's power consumption control coordinates operation of the Enhanced Intel SpeedStep mode as well as switching between the C-states, which results in low supply voltage operation for Core Duo chips and minimum heat dissipation in the active state

• The advanced Intel Deeper Sleep technology with the Dynamic Cache Sizing feature - implies that the core voltage on the processor can be reduced to a level even less than that defined by the Deeper Sleep technology. Dynamic Cache Sizing – a new power-saving mechanism that allows the Intel Smart Cache system to disengage the system memory dynamically on demand or whenever it is not in use
• Support for the new generation of supply voltage control system - Intel Mobile Voltage Positioning (Intel MVP VI) optimized for 2-core mobile chips
• Intel Advanced Thermal Manager using the Digital Temperature Sensor. Intel Advanced Thermal Manager is in charge of a more precise control of thermal modes and more precise control of acoustic performance of the PC
• Support for Execute Disable Bit
• Intel Virtualization Technology - hardware extension for client and server systems, which combined with respective software allows to raise performance and efficiency of concurrent use of a number of corporate and user applications
• Options of the housing make: Intel Core Duo - Micro Flip-Chip Pin Grid Array (Micro-FCPGA), for 479-pin ZIF-connector (Zero Insertion Force), more known as mPGA479M, and Micro Flip-Chip Ball Grid Array (Micro-FCBGA) for assembly with soldering, Low Voltage and Ultra Low Voltage Core Duo - Micro-FCBGA